Full Description

Scope

This standard defines the syntax and semantics of the VHSIC Hardware Description Language (VHDL). The acronym VHSIC (Very High Speed Integrated Circuits) in the languagea??s name comes from the U.S. government program that funded early work on the standard.

Purpose

VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Since it is both machine and human readable, it supports the design, development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. This document is intended for the implementers of tools supporting the language and for advanced users of the language.

Abstract

Revision Standard - Active.VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language. (This standard incorporates open source. See https://opensource.ieee.org/vasg/Packages)

Product Details

Published: 12/23/2019 ISBN(s): 9781504463980, 9781504461351, 9781504461368, 9781504466189, 9781504466196 Number of Pages: 673 File Size: 1 file , 4.5 MB Redline File Size: 2 files , 25 MB Product Code(s): STDRL23872, STD23872, STDPD23872, STDPDRL23872, STDPL23872